A silicon single crystal wafer serving as a material for a semiconductor device can be generally fabricated by growing a silicon single crystal based on a Czochralski method (which will be also referred to as a CZ method hereinafter) and performing a process, e.g., slicing or polishing with respect to an obtained silicon single crystal.
In the silicon single crystal grown based on the CZ method in this manner, an oxidation induced stacking fault called an OSF that occurs in a ring-like shape may be produced when subjected to thermal oxidation processing (e.g., 1100° C. for two hours). It has been revealed that a fine defect (which will be also referred to as a Grown-in defect hereinafter) that is formed at crystal growth and adversely affects device performance is present besides the OSF.
Thus, in recent years, for example, Japanese Unexamined Patent Publication (Kokai) No. H11-79889 or Japanese Patent No. 3085146 discloses a single-crystal manufacturing method that is used to obtain a wafer in which such defects are reduced as much as possible.
FIG. 8 shows an example of a relationship between a pulling rate and a defect distribution when a single crystal is grown. This is an example where V/G as a ratio of a pulling rate V (mm/min) when growing the single crystal and an average value G (° C./mm) of an in-crystal temperature gradient in a pulling axis direction in a temperature range from a silicon melting point to 1300° C. is changed by varying the pulling rate V.
It is generally known that a temperature distribution in the single crystal is dependent on a structure in a CZ furnace (which will be also referred to as a hot zone hereinafter) and the distribution hardly varies even if a pulling rate is changed. Therefore, when the structure of the CZ furnace remains the same, V/G is associated with a change in pulling rate alone. That is, the pulling rate V and V/G approximately have a direct proportion relationship. Therefore, the pulling rate V is used for an ordinate in FIG. 8.
In a region where the pulling rate V is relatively high, vacancy type grown-in defects called COPs (Crystal Originated Particles) or FPDs (Flow Pattern Defects) considered as voids as an aggregation of holes, that are point detects called vacancies (which will be also referred to as Va hereinafter), are present in an entire crystal radial region, and this is called a V-Rich region.
When the pulling rate V is slightly reduced than this, OSFs are produced in a ring-like pattern from a periphery of a crystal, the OSFs shrink toward a crystal center as the pulling rate V is lowered, and the OSFs are finally annihilated at the crystal center.
When the pulling rate V is further reduced, a Neutral (which will be also referred to as N hereinafter) region where excess or deficiency of Va or interstitial point defects called Interstitial Silicon (which will be also referred to as I hereinafter) rarely occurs is present. It has been revealed that in this region an agglomerated defect like the COP or the FPD is not present or presence of a defect cannot be detected by a current defect detection method, since this N region is biased toward Va or I but has a saturated concentration or a lower concentration.
This N region is divided into an Nv region where Va is dominant and an Ni region where I is dominant.
When the pulling rate V is further reduced, I becomes supersaturated, defects of L/D (Large Dislocation: an abbreviation of an interstitial dislocation loop, e.g., LSEPD or LEPD) considered as a dislocation loop obtained by agglomeration of I are consequently produced at a low density, and this region is called an I-Rich region.
Under the circumstances, a single crystal pulled up while controlling V/G in a range where the N region can be formed in the entire region along a radial direction from the center of the crystal is sliced into wafers, and polishing each wafer enables obtaining a wafer having a structure where the entire plane in the radial direction becomes the N region and having extremely less defects.
For example, a wafer sliced out at a position A-A in FIG. 8 becomes a wafer having an Nv region in the entire plane as shown in FIG. 9(a). FIG. 9(b) shows a wafer sliced out at a position B-B in FIG. 8, and an Nv region is present at a wafer central portion while an Ni region is present at an outer periphery thereof.
FIG. 9(c) shows a wafer sliced out at a position C-C in FIG. 8, and a wafer having a wafer entire plane formed of an Ni region can be obtained.
It is to be noted that these wafers are just examples, and the Ni region may be present at the wafer central portion while the Nv region may be present at the outer periphery thereof in contrast to the example depicted in FIG. 9(b) depending on a hot zone and so on.
When a grown-in defect that is present in a V-Rich region or an I-Rich region appears on a wafer surface, an adverse influence, e.g., a reduction in breakdown voltage of an oxide film when an MOS (Metal Oxide Semiconductor) structure for a device is formed is given to device characteristics, and hence absence of such a defect on a wafer surface layer is demanded.
FIG. 10 schematically shows a relationship between V/G, a Va concentration, and an I concentration, and this relationship is called Voronkov's theory and means that a boundary between a vacancy region and an interstitial silicon region is determined based on V/G.
In more detail, a region where Va is dominant is formed when V/G is equal to or above a critical point (V/G)c, and a region where I is dominant is formed when V/G is equal to or below the critical point. That is, (V/G)c indicates a V/G value at which Va and I have the same concentration.
An I-Rich region in FIG. 10 is a region where an agglomerate of interstitial silicon point defects, i.e., a grown-in defect of L/D is generated since V/G is equal to or below (V/G)i and the interstitial silicon point defects I have a saturated concentration Ci or a higher concentration.
The V-Rich region is a region where an agglomerate of vacancies, i.e., a grown-in defect, e.g., a COP is generated since V/G is equal to (V/G)v or above and vacancies Va have a saturated concentration Cv or a higher concentration.
The N region means a neutral region ((V/G)i to (V/G)osf) where an agglomerate of vacancies or an agglomerate of interstitial silicon point defects is not present.
Further, an OSF region ((V/G)osf to (V/G)v) is usually present in adjacent to this N region.
Meanwhile, a silicon wafer usually contains approximately 7×1017 to 10×1017 atoms/cm3 (a conversion factor provided by Japan Electronic Industry Development Association (JEIDA) is used) of oxygen in a supersaturated state.
Therefore, when such a silicon wafer is subjected to a heat treatment in, e.g., a device process, supersaturated oxygen in the silicon wafer is precipitated as an oxide precipitate. Such an oxide precipitate is called a BMD (Bulk Micro Defect).
This BMD becomes a problem since it adversely affects device characteristics, e.g., a junction leakage when it is generated in a device active region in a wafer but, on the other hand, this BMD is effective since it functions as a gettering site that captures a metal impurity mixed during a device process when it is present in a bulk other than the device active region.
Therefore, in manufacture of a silicon wafer, a BMD must be formed in a bulk of the wafer, and a defect-free region (Denuted Zone; which will be referred to as a DZ layer hereinafter) where a BMD or a grown-in defect is not present must be maintained near the wafer surface that is a device active region.
In recent years, as a method for manufacturing a silicon wafer which has no BMD generated therein on a silicon wafer shipping stage but is designed to have a gettering capability with a BMD formed in a bulk deeper than a device active region while maintaining a DZ layer having no BMD near a wafer surface that is the device active region by performing a heat treatment in, e.g., a subsequent device process, a method for performing an RTP (Rapid Thermal Process) processing with respect to a silicon wafer (a rapid thermal annealing) is suggested (see, e.g., Japanese Unexamined Patent Publication (Kokai) No. 2001-203210, U.S. Pat. No. 5,401,669, or Published Japanese Translation No. 2001-503009 of the PCT International Application).
This RTP processing is a heat treatment method characterized in that a temperature of a silicon wafer is rapidly increased from a room temperature at a temperature-up speed of, e.g., 50° C./s in a nitride formation atmosphere, e.g., N2 or NH3 or a mixed gas atmosphere obtained by mixing such a gas with a nitride non-formation atmosphere, e.g., Ar or H2, the silicon wafer is heated and held at a temperature of approximately 1200° C. for several-ten seconds, and then it is rapidly cooled at a temperature-down speed of, e.g., 50° C./s.
A mechanism of forming the BMD by performing an oxygen precipitation heat treatment after the RTP processing will now be briefly explained.
First, in the RTP processing, injection of Va occurs from the wafer surface, for example, during maintenance of a high temperature of 1200° C. in an N2 atmosphere, and annihilation due to redistribution based on diffusion of Va and recombination with I occurs while cooling in a temperature range of 1200° C. to 700° C. at a temperature-down speed of, e.g., 50° C. As a result, Va is unevenly distributed in the bulk.
When, e.g., an oxygen precipitation heat treatment is performed with respect to the wafer in such a state, each oxide precipitate is clustered in a region having a high Va concentration, and the clustered oxide precipitate grows, thereby forming a BMD. When the oxygen precipitation heat treatment is performed with respect to the silicon wafer subjected to the RTP processing, a BMD having a distribution in a wafer depth direction is formed according to a concentration profile of Va formed in the RTP processing.
As above, a technology that forms a silicon single crystal consisting of an N region is developed to eliminate a crystal defect, e.g., a COP or an OSF that adversely affects device performance, or a manufacturing method using the RTP processing is carried out when manufacturing a silicon single crystal wafer having a DZ layer in a surface layer and having a BMD in a bulk region.
However, first, in a silicon single crystal wafer consisting of an N region, since an initial oxygen concentration is relatively low, oxygen precipitation required for gettering cannot be satisfactorily obtained in some cases. Further, even though an entire plane in a radial direction is the N region, an Nv region and an Ni region are usually mixedly present, oxygen precipitation hardly occurs in the Ni region including a relatively large amount of I, and prominent unevenness occurs in a radial distribution of a BMD density in some cases.
As means for solving such problems of oxygen precipitation in the N region, there is a method for injecting vacancies into a wafer by a high-temperature RTP and facilitating oxygen precipitation based on these vacancies.
However, when the RTP is performed with respect to a silicon single crystal wafer formed of an N region in which Nv and Ni regions are mixedly present, TDDB (Time Dependent Dielectric Breakdown) characteristics are decreased in a region where defects are detected when a high-sensitivity OSF inspection that performs heat treatments on two stage at 1000° C. for three hours and 1150° C. for 100 minutes is carried out even though this region is the Nv region or a region where an OSF is not detected in a regular inspection. This tendency is more prominent in a wafer having a diameter of 300 mm larger than 200 mm.
Moreover, for example, a method using a silicon single crystal wafer in which an entire plane in a radial direction is formed of an Ni region can be also considered, but a manufacture margin for the silicon single crystal is narrow, productivity is low, and a manufacturing cost is notably increased.